Samsung's Plan for Terabit Flash Memory

New fabrication technology improves memory capacity without increasing chip size.

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Researchers at Samsung, one of the leading producers of flash-memory chips, recently announced a new chip that can hold twice as much data as before, and without an increase in its footprint on a circuit board. They were able to double the data capacity by building chips with multiple layers of silicon, creating 3-D structures. At the International Electron Device meeting in San Francisco last week, lead researcher Soon-Moon Jung said that by combining today's chip-making processes with the new 3-D design, they could build a one-terabit flash chip composed of eight layers of silicon.
Flash memory is found in all sorts of gadgets, from mobile phones and USB drives to MP3 players and laptops (see "Flash for Laptops"). In recent years, it gained popularity because, unlike the spinning disks of magnetic hard drives, flash is a solid-state memory (made of silicon), making it less prone to damage. And, unlike other types of solid-state memory, such as random-access memory, flash is nonvolatile, meaning it can retain data without power.
Because flash-memory chips are made with silicon, their storage capacity has consistently increased, while chip size has shrunk. But, like microprocessors, flash memory will face fabrication hurdles in the next few years. Right now, the features on many flash-memory chips are about 60 nanometers wide. Some engineers estimate that today's lithography systems, used to pattern and carve out these features, will only be able to keep shrinking them until about 2009. And even then, the chips face physical limitations. Samsung's Jung says that with features smaller than 30 nanometers, electrical charges stored in a flash-memory cell will start to leak, meaning data will be lost.
So the Samsung researchers set out to find a way to use existing fabrication technology to increase flash capacity. Jung says that two elements were key: minimizing the amount of extra area used for their stacking architecture, and keeping the number of extra fabrication steps to a minimum, so as not to drive up costs.
The researchers turned to a process previously used at Samsung to make 3-D stacks of static random-access memory. The process uses a high-quality, single-crystal silicon substrate to build the first layer of memory cells. That layer is then used as a foundation on which to build a second layer, also composed of single-crystal silicon.
Essentially, a single layer of flash is analogous to a parking lot: electrons fill up memory cells much as cars fill up parking spots. Adding another layer of silicon increases the data capacity just as a two-story parking garage can hold more cars than a one-story parking garage can.
The trouble with this 3-D layering method is that it tends to take up space on the first layer, which could be used as memory cells, says Vivek Subramanian, professor of electrical engineering at the University of California, Berkeley. The only way to grow a layer of crystalline silicon is by using another silicon layer as a seed, he says. Growing this second layer requires opening up "windows" in the first layer, potentially taking away space that could be used to store data.
By Kate Greene

Read article at techreview.com


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